1. Field of the Invention
This invention relates generally to a forward error correction (FEC) system and, more particularly, to an electronic equalizer providing auto feedback of both decision threshold and phase offset adjustments for the decision circuit in an optical receiver of an optical transmission network as well as adjustment of tap weight settings for an equalizer located in the optical receiver.
2. Description of the Related Art
Forward error correction (FEC) systems are used in optical transmission networks to provide for correction of received data. Intersymbol interference (ISI) occurs along the transmission span or link. As is known in the art, error correction codes operate on groups of information or data bits called symbols where each symbol may be a group of bits or a byte, for example. The symbols transmitted in predefined time periods eventually spread or overlap into one another due to optical impairments in the transmission lines, such as group velocity dispersion (GVD), as well as due to other system impairments such as interference between DWDM transmitted optical signals, properties of the transmitter, the particular fiber medium or other distortions that may result in data errors in data signal recovery at the optical receiver. As known in the art symbols are bytes of data used in multilevel threshold network systems. In this disclosure, discussion is limited to single threshold systems involving O/E conversion or E/O conversion of a serial data bit stream. Thus, it equates to symbols where a symbol is one bit. In either case, the invention as describer herein is applicable to either type of system using symbols or bits for data to be generated and transmitted over an optical link.
The distortion and degradation of the transmitter optical signal is expressed as the ratio between the erroneous bits counted at the optical receiver over the total number of bits received at the receiver from the optical transmitter and is called the bit error rate or BER.
As is known in the art, a FEC code is used to encode the data on the transmitter side for transmission along with the optically transmitted data. FEC provides for error correction of data transmitted based upon algorithms which correct for errors detected in the received coded data. Thus, FEC is an error correction approach based upon general comparisons between transmitted and received FEC code. The error counts employed in correction of transmitted data, already available for accomplishing error correction on the received data, are also readily available in many FEC systems to be employed for adjusting eye pattern operational parameters through various equalization techniques. For example, the error count rates may be employed to adjust for threshold level in the decision circuit as taught, for example, in U.S. Pat. No. 6,513,136. As reported in the art, the eye pattern or the eye closure diagram of transmitted data is employed for evaluating transmission performance and is deployed for data regeneration at the optical receiver. Such an eye diagram reveals the extent of signal degradation based upon the extent of eye closure. By monitoring the eye closure, the optimum slicing threshold and sampled phase (timing) with each bit can readily be determined.
There has been much interest in the deployment of electrical signal processing techniques utilized at optical receivers in optical transmission networks to reduced or otherwise suppress the effects of signal distortion, e.g., group velocity dispersion (GVD) including both chromatic dispersion (CD) and polarization mode dispersion (PMD) and intersymbol interference (ISI). To compensate for threshold or amplitude distortions of the received signal as well as phase distortions introduced in signal transmission, equalizers are employed which are time based filters which operate nonlinearly as well as linearly on these distortions to provide for a much improved decision circuit as to what level (threshold) and where within each bit period (time) a decision should be made to determine if a bit is a logic “1” or a logic “0”. In general, for compensation of PMD and CD, a transverse filter (TF) is deployed for linear compensation which is also referred to as a feed forward equalizer (FFE). The FFE is basically a tapped delay line where the signal to be corrected is delayed by various amounts and multiplied by predetermined weights and then added together as an output. The delays and the choice of weights determine the transfer function of FFE filter. Generally, the FFE divides the signal into segments, renders copies of the segments, and delays the segment copies by constant delay stages, ΔT, such as T1, T2, T3, etc, where T is the bit period of the received signal, and then superimpose the delayed signal segments at an output to the decision circuit which may be included in the clock and data recovery (CDR) circuit of the optical receiver. The FEC system may further include an adaptive phase and threshold circuit that dynamically determines the voltage threshold and phase (time position) within each bit slot in which a bit is to be determined as a “1” or “0” within a bit period, T, which is visually depicted by the eye pattern. The delays, ΔT, may also be multiples of the bit period T and the tap weights, such as C0, C1, C2, C3, etc., are dynamically adjusted to maximize the received signal quality. The FFE may also be combined with a decision feedback equalizer (DFE) which is a nonlinear filter to provide for further cancellation of signal distortion. The concatenation of the FFE with the DFE provides for improved error correction and lowering of the bit error rate (BER). A DFE comes after the decision circuit and after a decision has been made on whether a bit slot contains a “1” or a “0” and a bit pattern or sequence that this particular bit induces on future bits of the same bit pattern characteristic may be subtracted out before a decision is made on any future bits experiencing the same induced error characteristic. Similar to the tap weights of the FFE, the feedback amplitude of the DFE is dynamically adjusted rather than a DFE time delay as in the case of the FFE.
A byproduct of the equalizer is the ability to count corrected error bits 1's or 0's at the FEC decoder and employ theses corrected error counts for determining the eye opening pattern and/or for determining adjustments to threshold and phase (timing).
There are several different approaches to equalization and a few are mentioned here. One approach is to determine the slicing threshold and sampling phase through the deployment of a BER map formed from several sampled points or positions and then determine the optimized sampling point. The approach is likened to a target approach relative to eye threshold and phase. See, as an example, U.S. Pat. No. 6,519,302.
Another approach is counting of corrected errors of 1's and 0's and using a kind of look-up table indicative of the amount and direction of correction relative to the eye pattern. The number of corrected 1's and 0's are summed up and provide a description of the behavior of distortions and impairments of the transmission channel. From this description, a correction value can be determined from a look-up table which is added to the incoming data signals to be corrected. See, as an example, published U.S. patent application Pub. No. 2002/0181573.
In a still more recent published U.S. patent application Pub. No. 2003/0011847, published Jan. 16, 2003, an ASIC chip includes a transversal filter, DFE and CDR circuits with a time domain error circuit all on the same chip and adapted to measure the four orthogonal eye pattern positions (top error, bottom error, left error and right error) based upon the accumulated corrected error count which is employed via a digital signal processor (DSP) to continuously adjust the decision threshold and sampling time in the decision circuit for each bit.